The foundry development of integrated photonics has revolutionized today’s optical interconnect and data centers. Over the last decade, we have witnessed the rising of silicon nitride (Si3N4) integrated photonics, which is currently transferring from laboratory research to foundry manufacturing. The development and transition are triggered by the ultimate need for low optical loss offered by Si3N4, which is beyond the reach of silicon and III-V semiconductors. Combined with modest Kerr nonlinearity, tight optical confinement, and dispersion engineering, Si3N4 has today become the leading platform for linear and Kerr nonlinear photonics, and it has enabled chip-scale lasers featuring ultralow noise on par with table-top fiber lasers. However, so far all the reported fabrication processes of tight-confinement, dispersion-engineered Si3N4 photonic integrated circuits (PICs) with optical loss down to few dB/m have only been developed on 4-inch (100 mm diameter) or smaller wafers. Yet, to transfer these processes to established CMOS foundries that typically operate 6-inch or even larger wafers, challenges remain. In this work, we demonstrate the first foundry-standard fabrication process of Si3N4 PICs with only 2.6 dB/m loss, thickness above 800 nm, and near 100% fabrication yield on 6-inch (150 mm diameter) wafers. Such thick and ultralow-loss Si3N4 PIC enables low-threshold generation of soliton frequency combs. Merging with advanced heterogeneous integration, active ultralow-loss Si3N4 integrated photonics could pave an avenue to addressing future demands in our increasingly information-driven society.
Figure 1.Process flow and sample images of the 6-inch Si3N4 foundry fabrication process. (a) Photograph of dozens of Si3N4 chips on a 6-inch wafer, which contains microresonators of different FSR and meter-long spirals. (b) Optical micrograph showing a curved bus waveguide slowly approaching a 100-GHz-FSR microring resonator. (c) SEM image showing the Si3N4 waveguide core with SiO2 cladding. The TE00 mode is plotted, showing tight confinement in the Si₃N₄ waveguide core. (d) DUV subtractive process flow. WOX, wet oxide (SiO2).
Figure 1(a) presents a photograph that shows dozens of Si3N4 chips on a 6-inch wafer, which contains microresonators of different free spectral ranges (FSRs) and meter-long spirals. Figure 1(b) presents an optical micrograph that shows a curved bus waveguide slowly approaching a 100-GHz-FSR microring resonator for light coupling. This coupler design can increase coupling strength and ideality. Figure 1(c) presents a scanning electron microscopy (SEM) image that shows the actual Si3N4 waveguide cross-section with 85° sidewall angle and overlaid fundamental transverse-electric (TE00) mode. The optical mode is tightly confined in the Si3N4 waveguide core with SiO2 cladding, enabling dispersion engineering and small bending radii.
The Si3N4 PIC is fabricated using the DUV subtractive process. Figure 1(d) shows the subtractive process flow widely used to fabricate PIC based on essentially any material, particularly Si3N4. First, a Si3N4 film is deposited on a clean thermal wet SiO2 substrate via low-pressure chemical vapor deposition (LPCVD). It is well known that LPCVD Si3N4 films are prone to crack due to their intrinsic tensile stress (typically 1.1–1.4 GPa). The film stress can be relaxed via thermal cycling during Si3N4 deposition in multiple layers, yielding zero cracks during our fabrication. After SiO2 deposition as an etch hard mask, DUV stepper photolithography is used to expose the waveguide pattern. Via dry etching, the pattern is subsequently transferred from the photoresist mask to the SiO2 hard mask and then into the Si3N4 layer to form waveguides. For superior etch quality and smooth waveguide sidewall, the etchant we use is CHF3 with added O2 to remove fluoride-carbon polymers as etch byproducts.
